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Raúl Mateos

Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms
Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution
Dual-Core Architecture for PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer
Finite Precision Analysis of FPGA-based Architecture for FBMC Transmultiplexers in Broadband PLC

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